The present invention relates to a semiconductor memory device and a method of manufacturing the same. Particularly, the present invention relates to a technique effectively applicable to a semiconductor memory device in which a memory cell is constituted of a reading MIS transistor formed on a main surface of a semiconductor substrate and a writing MIS transistor formed on the reading MIS transistor.
Recently, as a general large-capacity semiconductor memory, DRAM (Dynamic Random Access Memory) having a memory cell constituted of a MOS transistor and a capacitor (capacitor element) has been mainly used.
Also, as an alternative semiconductor memory to the DRAM, the inventors of this application have developed, what is called, a three-dimensional semiconductor memory called a gain cell constituted of two MOS transistors as described in Japanese Patent Application Laid-Open No. 2000-113683, in which a source-drain path of a reading MOS transistor is formed in a semiconductor bulk of a main surface of a semiconductor substrate, and a writing MOS transistor having a layered structure formed by laminating a source semiconductor layer, a channel forming semiconductor layer, and a drain semiconductor layer on the main surface of the semiconductor substrate in a vertical direction is joined onto a gate electrode of this reading MOS transistor. Since the gain cell is a memory cell having a three-dimensional structure, in which the gate electrode of the reading MOS transistor having an extremely small leak current is used as a storage node, the memory cell capable of stably operating at high speed can be provided. In addition, the memory cell is scarcely influenced by the leakage carrier from the semiconductor bulk based on alpha rays or the like, and the reduction of the stored charge amount can be repressed. Therefore, this memory cell can be used also as a non-volatile memory.
The conventional DRAM as described above is suitable to attain the fine fabrication and large capacity because the memory cell of the DRAM is constituted of the minimum components, that is, a MOS transistor and a capacitor.
In recent years, however, as measures for compensating the decrease of the stored charge amount caused by the fine fabrication of the memory cell, a DRAM has been required in which a capacitor arranged on a MOS transistor is made three-dimensional to expand the surface area thereof, alternatively, a deep trench is made on a substrate to form a capacitor therein. Consequently, fine processing thereof has become increasingly difficult.
Also, it is conceived that it is difficult to compensate the reduction of the stored charge amount even if the capacitor only is made three-dimensional. Therefore, the adoption of high dielectric (ferroelectric) materials such as strontium titanate (STO) and barium strontium titanate (BST) as a dielectric film of a capacitor has been currently under consideration. However, additional capital investment is required in order to introduce such novel, high dielectric (ferroelectric) materials into the manufacturing process, which may cause a problem of the increase in the manufacturing cost.
On the other hand, since the gain cell of the three-dimensional structure has a small leak current, a memory cell can be constituted of a capacitor having relatively small capacity. Therefore, the semiconductor memory device of high density and large capacity can be provided. The inventors of this application carried out the studies on the semiconductor memory device having the memory cell of the three-dimensional structure as described above so as to improve the structure and the manufacturing method thereof.
Therefore, it is an object of the present invention to provide a semiconductor memory device having a memory cell of a three-dimensional structure, which is easily made fine.
It is another object of the present invention to provide a technique for manufacturing the semiconductor memory device at low cost.
The above described and other objects and the novel characteristic of the present invention will be apparent by the description and the accompanying drawings of this specification.
Among the inventions disclosed in this application, the outline of the representing one will be described as follows.
A semiconductor memory device of the present invention includes a memory array region formed of a plurality of memory cells arranged in matrix on a main surface of a semiconductor substrate, wherein each of the plurality of memory cells includes:
a reading MIS transistor having a source region and a drain region formed on the main surface of the semiconductor substrate, and a first gate electrode formed above the main surface of the semiconductor substrate via a first gate insulating film; and
a writing MIS transistor, which is electrically connected to and arranged on the first gate electrode of the reading MIS transistor, the writing MIS transistor having a source region, a channel forming region, and a drain region formed to be a layered structure extending in a vertical direction to the main surface of the semiconductor substrate, and a second gate electrode formed on a sidewall of the layered structure via a second gate insulating film.
According to the device described above, the layered structure of the writing MIS transistor can be arranged so as to form a convex shape or a trapezoid shape on a part of a first gate electrode of the reading MIS transistor.
According to the device described above, since the memory cell is constituted of the reading MIS transistor and the writing MIS transistor having the vertical structure and arranged on the reading MIS transistor, the memory cell which can be easily made fine can be realized.
Also, since the writing MIS transistor is arranged on the first gate electrode of the reading MIS transistor, a pn junction of the semiconductor bulk is not connected to a storage node. Therefore, in the state where the writing MIS transistor is in the OFF state (cutoff state), the storage node is not affected by the leak current caused from the pn junction of the semiconductor bulk due to the influence of the alpha rays or the like. In addition, electrical leakage paths other than the source-drain path of the writing MIS transistor can be removed. According to the foregoing, the holding characteristic of the stored data can be improved without using the large-capacity capacitor.
Also, in the state where the writing MIS transistor is in the cutoff state (OFF state), since the stored data is held by the gate electrode of the reading MIS transistor, it is possible to increase a signal voltage by adding a gain to a memory cell. Therefore, high-speed reading of data is enabled.
According to a method of manufacturing a semiconductor memory device having the above-described memory cell structure of the present invention, the method includes the steps as follows. That is, (a) putting a channel forming region of each row between a pair of rows adjacent to each other in a memory array region of the main surface of the semiconductor substrate, and forming a plurality of element isolation regions so as to define the source region and the drain region of the reading MIS transistor;
(b) forming a first gate electrode of the reading MIS transistor and a layered structure such that the first gate electrode and the layered structure are arranged in matrix at positions corresponding to each row and each column and extend in the column direction intermittently, the first gate electrode being formed on the channel forming region of each row via the first gate insulating film such that both end portions thereof in the column direction terminate on the element isolation region, and the layered structure including a lower semiconductor layer constituting a source region of the writing MIS transistor deposited on the upper surface of the first gate electrode, an intermediate semiconductor layer constituting a channel forming region, and an upper semiconductor layer constituting a drain region;
(c) introducing impurities into the semiconductor substrate with using the layered structure and the element isolation region as a mask, thus forming a source region and a drain region of the reading MIS transistor;
(d) forming a first interlayer insulating film on the semiconductor substrate so as to fill a gap between the plurality of layered structures arranged in matrix;
(e) forming a first conductive layer so as to be electrically connected to an upper surface of the plurality of layered structures exposed from the first interlayer insulating film and so as to cover the upper surface of the first interlayer insulating film;
(f) performing the etching of the first conductive layer, thus forming a first bit line, which extends in the row direction across the upper surface of the plurality of layered structures positioned in each row and is electrically connected to each of the upper semiconductor layer of the plurality of layered structures;
(g) performing the etching of the plurality of layered structures positioned below the first bit line such that the width of the layered structure corresponds to that of the first bit line and until the etching reaches the first gate electrode of the reading MISFET, thus exposing sidewalls of each of the plurality of layered structures;
(h) forming a second gate insulating film on the sidewall of each of the plurality of layered structures exposed in the step
(g), thus forming a second conductive layer so as to cover the sidewall portion and the upper portion of the first bit line; and
(i) performing the etching of the second conductive layer, thus forming a second gate electrode of the writing MIS transistor, which extends in the column direction across the upper portion of the plurality of layered structures positioned in each column and covers each of the sidewall portions of the plurality of layered structures.
According to the manufacturing method described above, in the step (b), the layered structure of the writing MIS transistor is formed on the first gate electrode of the reading MIS transistor having end portions terminating on the element isolation regions. Therefore, even if the layered structure and the element isolation region are shifted in position from each other on the first gate electrode, since the first gate electrode certainly functions as a mask for the source and drain impurities in the impurity introduction step into the source region and drain region of the step (c), the introduction of the impurities causing the short-circuit between the source-drain is prevented.
According to the manufacturing method of the present invention, the layered structure of the writing MIS transistor is made by depositing lamination films of a semiconductor material, for example, polycrystalline silicon on a main surface of a semiconductor substrate by the CVD technique, and the layered structure thus obtained can be cut at a time on the first gate electrode of the reading MIS transistor by the patterning technique. Therefore, the layered structure of the writing MIS transistor, that is, the source-drain path can be easily formed.
According to the manufacturing method of the present invention, in the layered structure of the writing MIS transistor, the intermediate semiconductor layer constituting the channel forming region can be easily formed as the one including the two-layered film, that is, a semiconductor film and a tunnel insulating film by alternately depositing the semiconductor film and the thin insulating film serving as the tunnel film. By doing so, the leak current between the source and the drain can be reduced when the transistor is in the OFF state (cutoff state). In this case, if the semiconductor film constituting the intermediate semiconductor layer is made of the pure semiconductor having substantially no impurities therein, the leak current in the source-drain path when the writing MIS transistor is in the OFF state can be further reduced.
According to the method described above, a memory cell is realized by using only the already-existing materials and the process technique thereof and not using any novel material. Therefore, the semiconductor memory device having a fine memory cell structure can be realized at low cost.
Other characteristic of the present invention in addition to the foregoing will be further understood by the concrete description based on the embodiments below.